In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto or removed from a substrate surface. As layers of materials are sequentially deposited onto and removed from the substrate, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization also is useful in forming features an a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition or more simply as a polishing composition (also referred to as a polishing slurry), for selective removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface of the substrate with a polishing pad (e.g., polishing cloth or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
As the size of integrated circuits is reduced and the number of integrated circuits on a chip increases, the components that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Effective isolation between circuits is important for ensuring optimum semiconductor performance. To that end, shallow trenches are etched into the semiconductor substrate and filled with insulating material to isolate active regions of the integrated circuit. More specifically, shallow trench isolation (STI) is a process in which a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer is deposited to fill the trenches. Due to variation in the depth of trenches formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches. The dielectric material (e.g., a silicon oxide) conforms to the underlying topography of the substrate. Thus, the surface of the substrate is characterized by raised areas of the overlying oxide between trenches, which are referred to as pattern oxide. Pattern oxide is characterized by the step height of the excess oxide dielectric material lying outside of the trenches. The excess dielectric material is typically removed by a CMP process, which additionally provides a planar surface for further processing. As pattern oxide is abraded and planarity of the surface is approached, the oxide layer is then referred to as blanket oxide.
A polishing composition can be characterized according to its polishing rate (i.e., removal rate) and its planarization efficiency. The polishing rate refers to the rate of removal of a material from the surface of the substrate and is usually expressed in terms of units of length (thickness) per unit of time (e.g., Angstroms (Å) per minute). Planarization efficiency relates to step height reduction versus amount of material removed from the substrate. Specifically, a polishing surface, e.g., polishing pad, first contacts the “high points” of the surface and must remove material in order to form a planar surface. A process that results in achieving a planar surface with less removal of material is considered to be more efficient than a process requiring removal of more material to achieve planarity.
Often the rate of removal of the silicon oxide pattern can be rate-limiting for the dielectric polishing step in STI processes, and therefore high removal rates of the silicon oxide pattern are desired to increase device throughput. However, if the blanket removal rate is too rapid, overpolishing of oxide in exposed trenches results in trench erosion and increased device defectivity.
A need remains for compositions and methods for chemical-mechanical polishing of silicon oxide-containing substrates that will provide useful removal rates while also providing improved planarization efficiency. The invention provides such polishing compositions and methods. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.